We'll be using SystemVerilog for code, testbenches, and any formal we do.

Install

The toolchain is Xilinx Vivado 2019.2 WebPack edition. You can install for Linux or Windows. You will need an account to download the software. If you are a citizen of Cuba, Iran, North Korea, Sudan or Syria, please talk to me.

After install the base IDE, please install the patch to take you 2019.2.1.

Run the installer as root/admin and login with your account.

• when asked choose to install Vivado Design Suite (not Vitis, Lab Edition, etc...)
• when asked choose the "WebPack Edition" (the others cost money)
• uncheck the UltraScale, UltraScale+, and Zynq UltraScale(+) families
• leave Zynq 7000 and 7-series families enabled

Design Elements

Double Buffer

Allow non-sync updates to the primary buffer, then in a single cycle copy the primary buffer to the secondary

Register Files

Basically the FPGA should appear as a spi device, and we should formalize a register access scheme. Perhaps on byte [R/!W, Control/!Config, Addr]. This would let us have 64,Nbit register for each type. A read and write would each be 5 transactions (control byte, 4 data bytes).

Assignments

Will:

• ff sync
• async fifio
• spi slave
• fixed point div
• fixed point tc

Arthur:

• fifo - recommended starting design
• spi master
• fixed point add
• fixed point sub
• fixed point mul

Arvind:

• double buffer

Up-for-grabs:

• refactors and improve old modules
• contol register file
• parameter register file (infer bram)
• parameter register file access scheduling

Also:

• ADC
• IMU
• ClkDivider
• Fixed point cos/sin (v. hard)
• Matrix stuff/operations (hard)